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56 afleveringen, van nieuw naar oud
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Why Marvell Wants Lumentum: Vertical Integration in AI Optics With Cignal AI
30 oktober 2026 · 40 min
Marvell's potential acquisition of Lumentum is a strategic vertical integration play to capture the massive value optical components now unlock in the AI era. Andrew Schmitt and Scott Wilkinson of market research firm Signal AI join Austin and Vik to break down the deal's core drivers. They explain how Marvell could run the 'Broadcom playbook' by bundling DSPs and optics, even at the cost of competing with its own customers, and why Lumentum's future-facing assets like Optical Circuit Switches (OCS) and high-power lasers are just as critical as its current-gen transceivers. Lees meer
This episode is presented by Crusoe. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoe
Key Takeaways:
- The deal's driver is vertical integration, not securing laser capacity. Marvell wants to control the supply chain from chips to optics to co-design superior products for the fast-moving AI market.
- The economics have flipped. Optics margins have doubled from ~25% to nearly 50%, making them attractive for chipmakers to acquire — even if it means Marvell pays 20-30x what it might have cost years ago.
- Lumentum's real moat is manufacturing scale. While others can build a hundred 'unicorn' devices like 200G EMLs, Lumentum's advantage is its ability to produce them reliably by the million.
- The acquisition creates channel conflict. Marvell's DSP customers will now have to compete with a vertically integrated Marvell-Lumentum, a dynamic that has already pushed some players out of the coherent market.
- This is also a bet on future architectures. The deal secures Lumentum's critical assets for next-gen data centers, including Optical Circuit Switches (OCS) and high-power lasers for CPO and NPO.
- Lumentum has the capacity to do both. After a 4x expansion of its Indium Phosphide…
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How Intel Took EMIB From Science Fiction to High Volume: Intel Foundry's Ravi Mahajan
28 oktober 2026 · 46 min
Intel's EMIB technology represents a scalable, cost-effective advanced packaging solution that now serves as a core strategic differentiator for its foundry services. Ravi Mahajan, a distinguished engineer at Intel Foundry, joins Austin to detail EMIB's 20-year journey from a "science fiction" concept to a high-volume manufacturing reality. They discuss the principle behind EMIB, interconnect where you need it and only where you need it: small silicon bridges carry the fine-pitch die-to-die signals, while the organic substrate's thick metal still delivers power and everything else. They also cover its manufacturing advantages over CoWoS and Intel's forward-looking roadmap for active bridges and top-side optics. Lees meer
This episode is presented by Crusoe. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoe
"When first envisioned, this was almost science fiction because the bridge I was talking about is roughly half the thickness of an A4 sheet of paper. So imagine being able to manipulate tiny strips of silicon like that."
— Ravi Mahajan, Intel FoundryKey Takeaways:
- EMIB was invented to outpace organic packages, whose wire escape density at the die edge improved only about 10% per generation. The principle Ravi keeps returning to is interconnect where you need it and only where you need it: fine-pitch silicon in small local patches at the die edges, with the organic substrate's thick metal still carrying power and everything else. Fine wires are a poor way to deliver power anyway, and small bridges cut from a wafer keep the silicon cost down.
- Bringing EMIB from concept to production required the convergence of five distinct technologies, including a custom 4-layer silicon process and handling dies half the thickness of an A4 sheet of paper.
- Intel str…
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RF Over Plastic Is a Third Option Between Copper and Optics: Point2's Sean Park
23 oktober 2026 · 1 uur 6 min
A novel third option is emerging for data center interconnects between short-reach copper and power-hungry optics. Point2 CEO Sean Park joins Vik Sekar to explain his company's Active RF Cable (ARC) technology, which sends high-frequency radio signals over a flexible plastic waveguide. Park details how this approach targets the critical 5-10 meter "scale-up" problem for AI clusters, claiming significant advantages in cable density, power efficiency, and latency over existing solutions. Lees meer
This episode is presented by Crusoe. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoe
"The bandwidth limitation simply comes from the existence of electrons. And this plastic, it doesn't have electron. So, in terms of bandwidth, it is unlimited. Bandwidth is unlimited. So, once our silicon works, we don't have to really change the this cable at all. Just scale the silicon, then it will it will be used for higher data rate."
— Sean Park, Point2 TechnologyKey Takeaways:
- The interconnect choice is no longer just copper vs. optics. Point2's Active RF Cable (ARC) creates a third category, sending 100-200 GHz signals over a plastic waveguide for the 5-10 meter reach AI scale-up requires.
- The core density advantage is 4x over copper. ARC uses a single plastic core instead of a differential pair (2x gain), then sends two channels per core using frequency division multiplexing (another 2x gain).
- The power savings come from silicon simplicity. By avoiding the laser, DSP, and TIA of optical modules, a 1.6T ARC module consumes <10 watts (~5 pJ/bit), with a roadmap to <2 pJ/bit for co-packaged versions.
- The latency improvement is three orders of magnitude. Because it requires no DSP, ARC latency is in the sub-nanosecond range — 1,000x better than DSP-based optical sol…
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MicroVCSELs vs MicroLEDs, a MicroExplainer
20 oktober 2026 · 39 min
Austin Lyons and Vik Sekar host a micro-explainer on the two competing micro-emitter technologies for AI interconnects: microLEDs and microVCSELs. They break down Credo's surprising pivot at OCP from its microLED acquisition to a microVCSEL product, revealing the core physics that give microVCSELs superior speed and reach. The episode establishes the technical reasons why the industry is converging on microVCSELs for the critical 5-50 meter gap in AI data centers. Lees meer
This episode is presented by Crusoe. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoe
Key Takeaways:
- The new battleground for AI interconnects is the 5-50 meter "reach gap"—too long for copper cables limited to ~7 meters, but too short for expensive, supply-constrained InP long-reach optics.
- MicroLEDs are limited by physics to ~3-5 Gbps over 5 meters. Their broad light spectrum causes "chromatic dispersion," smearing the signal and creating a hard ceiling on speed and reach.
- To achieve high bandwidth, microLEDs require massive parallelism—bundling ~300 slow lanes to hit 1 Tbps—which introduces significant manufacturing complexity in coupling hundreds of fibers.
- MicroVCSELs solve this, hitting 50 Gbps+ over 50 meters. Their "stimulated emission" physics creates a narrow, focused beam that suffers less from dispersion, enabling 10x the speed and reach of microLEDs.
- The supply chain is a key advantage. MicroVCSELs use a mature Gallium Arsenide (GaAs) process on 8-inch wafers, shared with cell phones, giving them a cost and scale advantage over exotic InP optics.
- MicroLEDs' niche is extreme heat. Their Gallium Nitride (GaN) material is highly temperature-insensitive, making them a candidate for very short-reach, high-reliability optics inside a hot server tray.
Chapters:
0:00… -
AI Inference Is a Data Movement Problem: Microsoft's Saurabh Dighe on Maia 300
15 oktober 2026 · 49 min
Microsoft's Maia 300 is a fully co-designed system, optimized to solve the memory-bound "data movement problem" of emerging agentic AI workloads. Lees meer
Saurabh Dighe, Corporate VP of Azure Hardware Systems at Microsoft, sits down with Austin to detail the architecture, from its TSMC N2P chiplet design enabling 18 TB/s of HBM4 memory bandwidth to its use of AI agents for automated kernel optimization.
They discuss how this full-stack approach aims to maximize intelligence per watt and per dollar for Microsoft's planet-scale services.
This episode is presented by @CrusoeAI. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoe
Key Takeaways:
- Microsoft views AI inference as a data movement problem, not a compute problem. The energy cost of moving data to feed the compute engine can be two orders of magnitude higher than the compute itself.
- The design of Maia 300 is driven by the shift from chat to agentic AI, which creates memory-bound workloads. The system delivers a 7x token throughput increase per rack over Maia 200, with a 5x increase in rack-level memory bandwidth.
- Maia 300 uses a chiplet architecture to "extend the shoreline" of its single TSMC N2P compute die. This allows it to accommodate eight HBM4 stacks, delivering 18 TB/s of memory bandwidth.
- Microsoft is using AI agents for "agentic kernel optimization" to automate the creation of low-level software. This strategy aims to bypass the manual optimization bottleneck and enable "Day-zero model availability" for new AI models.
- The system is built for deployment flexibility. While servers use direct liquid cooling, a rack-level "heat exchanger unit" allows the 167 kW racks to be deployed in traditional air-cooled data centers.
- The network is a two-tiered scale-up fabric built on standard…
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Synopsys’s Amazon Deal and GPT-Synopsys: Ravi Subramanian
8 oktober 2026 · 42 min
The demand for workload-specific hardware is forcing a strategic shift in the semiconductor IP business. Synopsys's Ravi Subramanian joins Austin to discuss why the company is moving to a new royalty-based model for its custom "application optimized IP," starting with a billion-dollar deal with Amazon. Ravi also unpacks Synopsys's partnership with OpenAI and its vision for AI "agent engineers" that augment human designers, while explaining why physics-based simulation remains the ultimate ground truth. Lees meer
This episode is presented by Crusoe. Try Crusoe's managed inference for open models with $5 in free credits: https://semidoped.com/crusoe
"in physics we trust is because at the end of the day, the ground truth to have the confidence, not hallucinate and be deterministic in your outcome is really what defines is a product going to be successful or not."
— Ravi Subramanian, SynopsysKey Takeaways:
- The hyperscaler IP model is shifting. Because 1-2 applications drive most revenue, companies like Amazon now demand custom “application optimized IP” instead of standards-based IP.
- Synopsys is adopting a new business model for this custom work: a license fee, a “customization fee” to prioritize scarce engineers, and for the first time, a royalty on the final chip.
- This new royalty model mirrors the Arm-Amazon partnership from a decade ago, aligning Synopsys with its customer’s 12-month design cycles and expanding its role to system-level bring-up.
- Synopsys’s AI strategy isn't just tools, but a new consumption model: customers can “hire” an AI agent engineer with a specific skillset, fitting directly into existing budgets and team structures.
- The GPT-Synopsys partnership with OpenAI is a turnkey service bundling a specialized LLM, the necessary compute, and forward-deployed engineers to solve the key adoption hurdles of model quality and compute scarcity.
- AI is for exploration, but physics is for verification. Accurately modeling a modern CFET requires 200…
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Every Muse User Gets 2 CPUs and 8GB in Meta's Cloud. Your Phone Already Has That
1 oktober 2026 · 51 min
The push to run AI agents on edge devices will not be driven by model labs or hardware vendors, but by service providers like Meta whose ad-based business models create a powerful financial incentive to offload massive cloud compute costs onto the user's own powerful-but-idle hardware. Austin Lyons and Vik Sekar break down why the failed "AI PC" push has given way to a new, economically-driven strategy for on-device AI. They discuss how Qualcomm's acquisition of Modular provides the key software layer and why the ultimate vision is an "ecosystem of you" where the device acts as a context-aware orchestrator between local and cloud compute. Lees meer
This episode is presented by Crusoe. Try Crusoe's managed inference for open models with $5 in free credits: https://semidoped.com/crusoe
"[Model Labs] business model is we make money when we do inference in the cloud. And yet we are saying, actually, there's a world where we would really like to just run this stuff locally... Meta's like, bro, I want to help you at the edge."
— Austin Lyons, ChipstratKey Takeaways:
- The driver for edge AI is a business model conflict. Model labs like OpenAI sell cloud inference; service providers like Meta see it as a massive cost center for their ad-supported agents like Muse.
- Your phone is an underutilized edge server. Its specs—like 8GB of RAM and 2 vCPUs of power—are comparable to the dedicated cloud VMs that services like Meta's Muse provision for each user.
- The "AIPC" push failed because it was a hardware-first strategy without a use case. Today's edge AI push is a software-first strategy driven by the need to cut cloud OpEx for mass-market agents.
- The role of the edge device is becoming a "context translation layer." It uses private data like location and biometrics to intelligently decide which AI tasks run locally versus in the cloud.
- Qualcomm's acquisition of Modular is a key strategic move. It positions the open-source Mojo language as the "write once, run anywhere" s…
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Flash Hit Its Physical Limit. ReRAM Is the Replacement: WeeBit Nano's Ilan Sever
29 september 2026 · 57 min
As embedded flash hits a physical and economic scaling wall below 22nm, a new on-chip memory is needed. Ilan Sever of WeeBit Nano joins to explain how Resistive RAM (ReRAM) is positioned to become the new standard by offering a low-cost, high-endurance alternative. Ilan details how ReRAM's simple back-end-of-line integration, automotive qualification, and future applications in AI in-memory compute create a compelling replacement for the incumbent technology. Lees meer
"In geometries below 28 or 22 nanometer, flash reached its physical limit, actually. So physically you cannot implement embedded flash anymore and the industry had been looking for alternative technologies for a few decades now."
— Ilan Sever, WeeBit NanoKey Takeaways:
- The inflection point for on-chip memory is physical. Embedded flash cannot scale below the 28/22nm node because its floating gate becomes too small to reliably hold charge.
- The economic problem with eFlash is its 25-30% cost increase, a result of adding 8-10 extra masks to a standard CMOS process—a non-starter for cost-sensitive MCUs.
- ReRAM's manufacturing advantage is its simplicity. It's built in the back-end-of-line (BEOL) metal layers, adding only two masks and not interfering with the sensitive transistors below.
- The physics are different: ReRAM isn't storing charge, it's changing resistance by using voltage to form or dissolve a conductive filament of oxygen vacancies in a dielectric.
- Automotive qualification is the key market validation. WeeBit's ReRAM is qualified for the AEC-Q100 standard and demonstrates 100,000 write cycles—10x that of typical eFlash.
- The business model isn't just a recipe; it's a full IP module with the bit cell, analog circuits, digital logic, and programming algorithms, which is what SoC designers actually need.
- Beyond replacing flash, ReRAM (as a memristor) is a foundational technology for future in-memory compute (IMC) AI accelerators that perform calculations inside the memory to save pow…
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Qualcomm's Durga Malladi: HBC vs HBM, Dragonfly AI 250, and Winning on TCO
24 september 2026 · 21 min
Qualcomm re-entered the data center inference market late — competitive GPUs, XPUs, and custom accelerators are already out there. Durga Malladi (EVP/GM, Technology Planning, Edge & Data Center) explains why they didn't build another me-too accelerator and instead placed a differentiating technical bet: High Bandwidth Compute (HBC). Lees meer
The difference between HBC and HBM: HBM is stacked DRAM that shuttles data across wide buses to a separate accelerator — very high bandwidth, but expensive and power-hungry. HBC bonds stacked DRAM directly on top of a custom logic die using wafer-on-wafer techniques, so a lot of the compute runs literally next to memory. The result is lower latency and lower power per bit — and 18x effective bandwidth on the AI 250 versus the AI 200 at the SAME 768 GB LPDDR capacity and the SAME 160 kW per rack.
Why the late-mover bet works: Qualcomm's differentiation isn't just architectural. Their foundry and memory-vendor relationships let them credibly promise the multi-megawatt-to-gigawatt supply hyperscalers need. Memory vendors are developing their own HBC-equivalent variants as partners rather than pure competitors, and Qualcomm expects the two technologies to co-evolve. Silicon is back in the lab; proof points land in Q1/Q2 2027.
Chapters:
0:00 Introduction
2:49 The Memory Wall Problem
8:05 HBC Physical Architecture
9:33 HBC vs. Custom HBM
11:50 Silicon Proof Points Coming
12:08 Managing Thermals
13:34 Dragonfly AI 250
14:48 Trillion-Parameter Model on One Card
16:56 Tokenomics and TCO
18:26 Why TCO is Key
19:26 Manufacturing at ScaleFollow Chipstrat:
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Pacing AI Means More Compute, Not Less
18 september 2026 · 37 min
The debate over "pacing" AI for safety is a red herring, as the practical outcome of more safety work is not a slowdown but a net increase in demand for compute hardware. Austin Lyons and Vik Sekar unpack Dario Amodei's call to slow down frontier AI development, arguing that the true governors on AI are not voluntary agreements but physical data center bottlenecks and geopolitical realities. They conclude that the push for more safety and interpretability will ultimately drive more sales of both training (GPUs) and inference (XPUs) hardware. Lees meer
Today's sponsor is G2i — expert training data, evals, and RL environments for AI labs: https://fandf.co/4wZvKHS
Chapters:
0:00 Introduction: Pacing AI
1:36 Recapping Dario Amodei's Essay
7:42 Hot Take: Anthropic vs. OpenAI
11:34 The John Deere Playbook
15:22 The Problem with Interpretability
17:53 Pulling the Plug
19:03 The Real Bottleneck: Data Centers
22:03 The Geopolitical Blind Spot
23:41 Counter-narratives: Meta & Open Source
27:26 The Investment Thesis: Pacing Increases Compute
32:29 The Financial System Analogy
36:05 AI Safety as the New CybersecurityFollow Chipstrat:
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TSMC Will Buy High NA After All: ASML's New 6x12-Inch Mask
14 september 2026 · 50 min
The emergence of user-friendly AI agents is creating massive new hardware demand, which in turn is forcing the semiconductor industry into a complex, multi-year transition to High NA EUV lithography and an entirely new 12-inch photomask standard. Austin Lyons and Vik Sekar unpack the physics and economics of ASML's move to High NA, explaining why it necessitates a shift from 6-inch to 6x12-inch masks and what this means for the timelines of TSMC, Intel, and Samsung. Lees meer
"This is where you have to get the whole supply chain coordinated around this. And this is why you really ultimately need ASML's biggest customers to stand up and say, 'We're going to buy this.'"
— Austin Lyons, ChipstratKey Takeaways:
- ASML's High NA EUV (0.55 NA) solves resolution but creates a new problem: anamorphic optics (4x by 8x demagnification) cut the exposure field in half, effectively doubling the cost per wafer.
- The industry's fix for High NA's halved output is a new 6x12-inch photomask standard — the 12-inch dimension compensates for the 8x demagnification, restoring the full 26mm x 33mm reticle size.
- This shift to 12-inch masks is a full supply chain problem, which is why TSMC is waiting until 2030 for high-volume manufacturing while the ecosystem matures over the next 5-7 years.
- Intel's aggressive first-mover strategy on High NA — with over 1 million wafers processed to date — is a direct reaction to its disastrous delay in adopting the previous generation of EUV.
- Nearly 30% of ASML's revenue comes from recurring services (€2.8B of €9B in Q2), giving it a more stable financial profile than a typical equipment manufacturer.
- The new wave of AI agents (Astra, Muse, Instinct) is moving from simple instruction-following to proactive partnership, creating hundreds of millions of new users for server CPUs and memory.
- Integrating AI agents into ubiquitous text platforms like WhatsApp is key for mass adoption, as it solves the 'blank text box problem' for non-technical user…
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OpenAI’s Jalapeño! Feeling Hot Hot Hot!
27 augustus 2026 · 55 min
Austin and Vik react to OpenAI's Jalapeño announcement at Hot Chips. Plus extra spicy questions like should OpenAI sell it, how much of this was AI-written RTL, and where is Anthropic's chip? Lees meer
Key Takeaways:
- The chip's core design philosophy is "dark silicon is cheaper than idle accelerators" — using one balanced chip and power-gating unused blocks is more efficient than a two-chip (e.g. GPU + LPU) solution.
- The unprecedented nine-month RTL-to-tapeout cycle was enabled by AI for EDA tools, serving as a wake-up call that small, expert teams can now develop Rubin-class chips in under a year.
- Jalapeño's key innovation is a NUMA-style architecture that gives each accelerator a local HBM slice, solving the memory contention that throttles performance in unified memory systems.
- OpenAI chose Broadcom's ESUN for its scale-up network to connect 128 chips in the rack at 600 GB/s and up to 2,048 chips across 16 racks at 200G --- all scale up!
- The design's "regret factor" principle justifies generality — the opportunity cost of being unable to support a future model is far higher than the marginal cost of adding hardware flexibility upfront.
Chapters:
0:00 Hot Chips Reaction
2:32 Designing for User Experience
11:16 A Generalized Inference Chip
14:18 The Foundry-IDM Analogy
18:42 The 'Regret Factor'
21:02 The 9-Month Design Cycle
23:45 Challenging the Two-Chip Solution
35:08 Solving HBM Underutilization
36:46 The NUMA Architecture Solution
39:28 System-Level ESUN Networking
42:06 Dark Silicon vs. Idle Accelerators
49:08 A Wake-Up Call for the Industry
52:59 Where's Anthropic's Chip?Follow Chipstrat:
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Grok Bots and How CPUs are used in Agentic AI
24 augustus 2026 · 45 min
The rise of user-friendly agentic AI platforms will create a massive new demand category for dedicated, high-core-count "agentic CPUs" to execute tasks in parallel, fundamentally reshaping the server CPU market beyond just feeding GPUs. Lees meer
Key Takeaways:
- The 'Mac Mini Craze' wasn't about having a GPU on your desk — it was also about security, as users needed a sandboxed machine to run untrusted agent code like OpenClaw, a problem cloud VMs solve too.
- In AI servers, the GPU is the 'genius' doing the thinking, while the host CPU is the 'assistant' whose primary job is keeping the GPU fed, requiring high single-core performance.
- Agentic tasks create a 'spillover' of parallel work that overwhelms the host CPU, creating a new demand category for dedicated, high-core-count 'agentic CPUs' in separate racks.
- The procurement decision for agentic CPUs becomes about cost-per-core, or 'cost per employee' — balancing core count (like AMD's 256-core chips) against single-core speed.
- Intel's P-rack (Performance) and E-rack (Efficiency) offerings are a direct response to this need for heterogeneous CPU solutions tailored to different agentic workloads.
- The mass adoption of agentic AI could create demand for a billion new CPU cores in the cloud, driven by the convenience of 'easy button' platforms over self-hosting.
- A key bottleneck to this heterogeneous future is the orchestration software needed to schedule jobs across different CPUs and accelerators from multiple vendors.
Chapters:
0:00 Introducing Grok bot
3:45 Grok bot's Cloud VM Architecture
6:28 The 'Mac Mini Craze' Explained
14:38 Three CPU Deployment Models
16:02 GPU as Genius, CPU as Assistant
21:36 The Limits of the Host CPU
25:20 The 'Office Building' Analogy
29:09 Cost-Per-Core is the Metric
31:20 Intel's P-rack and E-rack
37:32 The Orchestration Bottleneck
40:19 Where Grok bot's VM Lives
44:22 The Unanswered QuestionFollow Chipstrat:
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Tensordyne's R K Anand: HPE Juniper Fabric, Logarithmic Math, MoE Inference, Air Cooling, 3nm
18 augustus 2026 · 56 min
Tensordyne co-founder and CPO R K Anand joins Austin to discuss the company's strategy for disrupting AI inference. RK explains how Tensordyne combines power-efficient logarithmic math with a battle-hardened networking fabric from partner HPE Juniper. The result is a high-density, air-cooled system designed to efficiently run massive Mixture-of-Experts models in existing data centers. Lees meer
Key Takeaways:
- The core innovation isn't just log math, it's the patented method for accumulation. This turns expensive multiplications into cheap additions, freeing die space for a massive on-chip SRAM cache.- Networking is a partnership, not a project. Tensordyne leverages HPE Juniper's 7th-gen router fabric, skipping development cycles to get a 1-2 microsecond latency solution ideal for random MoE traffic.
- The power and density claims are radical. By combining log math silicon with an air-cooled fabric, Tensordyne packs 72 chips into a 13U chassis at just 30 kW — a quarter of the space and power of an NVL72.
- One go-to-market advantage is air cooling. The 30 kW, 19-inch rack system can be deployed in existing 'brownfield' enterprise and telco data centers that cannot support liquid cooling.
- Partnerships de-risk the aggressive timeline. Broadcom provides access to TSMC 3nm and HBM, while strategic investor HPE Juniper provides the carrier-grade fabric with 'five nines' reliability.
Chapters:
0:00 Introducing Tensordyne
5:32 The Juniper vs. Cisco Playbook
11:29 Origin Story: Automotive Power Constraints
15:37 The Secret Sauce of Log Math
18:02 Pivoting to the Data Center
22:08 Leveraging a Router Backplane for AI
27:22 Why Router Fabrics Suit MoE Models
34:12 The Three Phases of Inference Hardware
37:40 How One Chip Handles Pre-fill & Decode
40:34 The 'Too Good to Be True' System Specs
43:31 Go-to-Market: The Air-Cooled Advantage
48:21 De-risking with Strategic Partnerships
52:37 Solving the Software Problem with AIFollow Chipstrat:
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NEWS TAKE: China's Optical Ban, Volta's $10B Anthropic Deal, AMD's Earnings
11 augustus 2026 · 35 min
Austin Lyons and Vik Sekar break down three stories that hit semis last week. They analyze a proposed US ban on Chinese optical transceivers that threatens to cut off 50% of the global supply, the market's reaction to AMD's surprise $800M CapEx spend despite strong earnings, and how a new company called Volta Infrastructure landed a $10B compute deal with Anthropic by pioneering a new financial model for AI. Lees meer
Key Takeaways:
- The proposed ban on Chinese optical transceivers is based on a flawed security rationale—the components are simple signal converters, not a meaningful vector for malware.
- A ban would be self-defeating, as it would cut off the ~50% of global transceiver supply assembled in China, creating the very data center disruption it claims to prevent.
- AMD's successful pivot to a data-center-first company (58% of revenue) is being scrutinized for its high CapEx—$800M vs an expected $200-300M—revealing the hidden costs of securing supply.
- Nvidia's use of on-chip SRAM for inference's decode phase highlights a strategic gap for AMD, which lacks a compelling SRAM-based solution to compete on disaggregated workloads.
- Volta Infrastructure's $10B deal with Anthropic is an innovation in finance, not tech; it applies low-cost 'infrastructure debt' to AI compute by framing clusters as predictable 'token factories'.
- The Volta deal was necessary because all existing CSP capacity is allocated; it acts as a 'clean balance sheet' SPV to secure low-cost debt for Anthropic's new, dedicated Nvidia capacity.
Chapters:
0:00 Intro: News Take Format
0:40 The China Optical Ban
4:02 A Flawed Security Rationale
11:30 Market & Supply Chain Impact
15:07 Investment Paralysis
15:52 AMD's Earnings Scrutiny
24:46 AMD's Missing SRAM Strategy
25:33 Volta's $10B Anthropic Deal
28:55 Volta's 'Toll Road' Model
32:19 Why the Volta Deal Was Necessary
33:38 The 'One Customer' Counterpoint
34:27 Wrap: Tech & Financial InnovationFollow Chipstrat:
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GlobalFoundries Thomas Barber: CPO, Silicon Photonics, 300mm, SiGe, OCI, NRZ
7 augustus 2026 · 40 min
The physical limits of copper are forcing a shift to optical interconnects in AI data centers. Austin sits down with GlobalFoundries' Thomas Barber to unpack why GF thinks it can lead that transition twice over: once with its long-running silicon photonics platform, and again with the specialty Silicon Germanium process the industry needs to drive it. Lees meer
"The enemy to me right now is copper. I'm trying to beat copper, right? If TSMC wins and we win, that's great because we're both displacing copper. And until all the copper is gone, there's plenty of market to go around."
— Thomas Barber, GlobalFoundriesKey Takeaways:
- Copper's usable range halves every time the data rate doubles, and 200 Gbps/lane inside a rack-scale AI cluster is already past the point copper can handle.- CPO's real win isn't speed, it's power: saving 20-25 pJ/bit frees part of a data center's fixed 50-100 MW budget to go toward compute instead of moving bits.
- GlobalFoundries leads photonics revenue for an unglamorous reason: it moved to 300mm wafers early, which yields 2.25x more die per wafer than the 200mm lines rivals still run.
- CPO can end up more reliable than the pluggables it's replacing, not less, because it deletes the physical plug connector, and dust at that connector is the leading cause of field failures.
- The OCI MSA picks NRZ over faster PAM4, deliberately going wide and slow, because NRZ's native bit error rate is a million times lower, which simplifies the receiver and cuts power.
- GlobalFoundries stacks two specialty processes into one edge: micro-mirror couplers on the photonic side, and Silicon Germanium transistors hitting 350-400 GHz on the electrical side driving them.
- The real competitor for silicon photonics isn't another foundry, it's copper itself — and that market is big enough that GlobalFoundries and TSMC can both win without taking share from each other.
Chapters:
0:00 GlobalFoundries in Photonics
1:21 GF's Photonics Strategy
3:02 GF's Market Leade… -
How Retimers Built an $80B Company: The Story of Astera Labs
1 augustus 2026 · 48 min
A retimer is a small, unglamorous chip. Astera turned it into a high-margin franchise. Austin and Vik cover why copper gives up at PCIe speeds, what a retimer does that a redriver can't, and how one H100 socket became a moat. Then Scorpio: can Astera take switch share from Broadcom? Lees meer
Key Takeaways:
- 30cm of PCB trace at Gen 5's 32 GT/s and the signal is gone. Signal integrity is an inside-the-server problem, not just a rack-to-rack one.
- Gen 6 swaps NRZ for PAM4. Four voltage levels instead of two — a third the eye height, ~9.5 dB of SNR gone.
- A redriver amplifies, noise included. A retimer recovers the clock and data, rebuilds the signal, and resets the jitter budget.
- Astera won H100 by shipping PCIe 5 retimers at volume first, then bundling COSMOS on top. The chip became a fleet telemetry sensor.
- Sticky socket: H100 carried straight into an Aries 6 design-in on Blackwell.
- Scorpio moves up the stack. Same signal conditioning IP, higher ASP, pointed at Broadcom's PCIe switch business.
- Astera granted Amazon a warrant — 3.26M shares at $142.82, vesting against up to $6.5B of purchases through 2033. Equity flowing to the customer, and it sizes the Scorpio P-Series commitment behind Trainium 2 and 3.Chapters:
0:00 The Astera Labs Franchise
3:32 The PCIe Copper Problem
6:53 Signal Smearing and Jitter
11:52 Eye Diagrams Explained
14:59 Equalization: Fixing the Signal
23:52 Redriver vs. Retimer
29:30 How Astera Won Nvidia
35:22 The Blackwell Scare
38:50 Scorpio: Moving into Switches
42:52 The UALink vs. Ethernet Battle
45:58 Taurus and Leo Product LinesFollow Chipstrat:
Newsletter: https://www.chipstrat.com
X: https://x.com/chipstratFollow Vik:
Newsletter: https://www.viksnewsletter.com/
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News Take: Hyperscaler CDS, SK Hynix Earnings, China's DUV
29 juli 2026 · 18 min
Austin Lyons and Vik Sekar break down the market's recent volatility. They discuss the rising fear around hyperscaler debt, visible in credit default swap (CDS) premiums, and the counter-argument that GPU ROI is actually understated. They then analyze the paradox of SK Hynix's massive stock drop despite record growth, and explain why China's new DUV lithography tool makes 3D chip stacking essential to their strategy. Lees meer
Key Takeaways:
* Hyperscaler debt fears are quantified by rising credit default swap (CDS) premiums, signaling investor nervousness that the AI CapEx firehose is shifting from cash flow to riskier debt.* The counter-take on debt is that hyperscalers are under-earning on GPU assets — as long-term contracts re-price to spot rates 2x higher, the hardware's ROI will justify the financing.
* SK Hynix's 20% stock drop despite 257% YoY revenue growth shows a market priced for perfection, where a small miss against consensus triggers a panic disconnected from fundamentals.
* The memory market paradox: commodity DRAM is currently more profitable than HBM because HBM's production is 3x less bit-efficient per wafer, consuming scarce supply while DRAM spot prices soar.
* China's reported immersion DUV breakthrough is equivalent to ASML's late 2000s-era technology, a step toward self-sufficiency but not a leap to the leading edge.
Chapters:
0:00 The Market Is Freaking Out
0:21 Hyperscaler Debt and Credit Default Swaps
3:56 The Counter-Take: Under-Earning on GPUs
6:18 SK Hynix: Record Growth, Market Carnage
8:10 The HBM vs. DRAM Profitability Paradox
10:35 Leverage, Retail, and Panic Selling
12:05 China's Immersion DUV Breakthrough
13:28 The Limits of DUV: 7nm and Multi-Patterning
14:14 Logic Folding and 3D Stacking
16:12 A Long Journey to Self-Sufficiency
17:05 Surviving Semiconductor CyclicalityFollow Semi Doped:
Get more of Austin and Vik daily, free: https://daily.semidoped.com/Follow Chipstrat:
Newsletter: https://www.chipstrat.com
X: https://x.com/c… -
Datacenter Interconnects: Copper vs. Optics, Nvidia's 78-Layer PCB, Co-Packaged Optics (CPO)
25 juli 2026 · 49 min
Vik Sekar and Austin Lyons tackle the biggest bottleneck in inference: moving data. They break down the three tiers of datacenter networking — scale up, scale out, scale across — and the core engineering trade-off at each layer: copper vs. optics. Topics include Nvidia's extreme measures to keep scale-up fabric electrical (a 78-layer mid-plane PCB), why Co-Packaged Optics is the "holy grail" everyone wants and no one can ship, and the serviceability problem standing in its way. Lees meer
Key Takeaways:
A single 72-GPU scale-up rack needs 5,000+ cables spanning ~2 km — at that density, the power and cost of every connection becomes a system-level constraint, not an implementation detail.
The scale-up rule is "copper when you can, optics when you must": each pluggable optical module adds ~30W, and with thousands of links in the fabric, that penalty compounds fast.
Nvidia is pushing copper past its usual limits with a 78-layer mid-plane PCB — 3x+ the layer count of a typical complex board — specifically to avoid paying the optics power tax in its scale-up fabric.
Scale-up isn't just a training problem. Frontier MoE models need 72-GPU domains to hit memory bandwidth targets, which pulls high-performance interconnect into the inference conversation.
Scale-up has the highest connection density of the three tiers, making it the largest TAM and the sharpest three-way fight between NVLink, UA-Link, and Ethernet.
Co-Packaged Optics could cut interconnect power by two-thirds — but a single failed laser could brick an entire multi-thousand-dollar GPU package, and that serviceability risk is what's keeping it on the roadmap instead of in racks.
Chapters:
0:00 The Biggest Problem in Computing
7:14 The Three Tiers of Networking
13:49 Scale Up: Copper vs. Optics
17:59 Front-End vs. Back-End Networks
22:12 The Physical Scale of Cabling
28:46 Nvidia's 78-Layer Mid-Plane
33:16 How Optical Transceivers Work
39:16 The Power Penalty of Pluggables
42:09 The Business of Speed Transitions
44… -
PicoJool's Al Yuen: The Case for GaAs VCSELs in Scale-Up Interconnects
16 juli 2026 · 49 min
Al Yuen, CEO of PicoJool, talks with Austin about using VCSELs for scale-up optical interconnects in AI data centers. Al explains why gallium arsenide (GaAs) supply is unconstrained while indium phosphide (InP) is limited, and how PicoJool can leverage existing supply chains to ship in the millions per month. They cover the roadmap from 1.6T to 12.8T, the trade-offs among 8×200G, 16×100G, and 32×50G, and the push to train the next generation of photonics engineers. Lees meer
The spec that changed is error rate. AI needs error-free links (10⁻¹⁰–10⁻¹² vs Ethernet's old 10⁻⁶) because GPUs act as one system — one error stalls the whole job.
Single-mode optics can't hit the volume. Built for ~100K city-to-city links; datacenters need millions/month — a 10–50× gap
GaAs vs InP is the whole supply story. VCSELs run on unconstrained GaAs; single-mode on constrained InP. 1M units: 8–10 weeks vs a sold-out 8–18 months.
One platform, three flavors to 1.6T: 8×200G "fast and narrow," 16×100G LPO low-power, 32×50G NRZ "slow and wide" — pick on power, cost, and BER.
12.8T needs no new tech — just more of the same: 64 channels (4×16 array in a finger-sized connector) × 200G, scaling channels, bi-di wavelengths, and lane speed.
Capacity isn't the time consuming part — qualification is. WIN runs ~1,000 wafers/week at ~240K VCSELs each, so 1M units = ~10 wafers. The wait is tier-1 (>6 mo) and tier-2 (~3 mo) quals.
Chapters:
0:00 Meet Al Yuen and PicoJool
2:29 Inventing the active optical cable
5:03 Engineering mindset, copper limits
8:43 Why VCSELs
13:45 Scale-up and bit error rate
20:09 Unconstrained vs constrained supply
21:53 Indium phosphide bottleneck
25:49 VCSEL design and foundry handoff
31:59 Product road map, 200G launch
34:16 Path to 3.2T and 12.8T
40:10 Ordering a million VCSELs
45:10 Ramp timing and training new engineersFollow Chipstrat:
Newsletter: https://www.chipstrat.com
X: https://x.com/chipstratFollow Vik:
Newsletter: https://www.viksnewsletter.com/
X: https://x.co… -
WEKA's Val Bercovici: KV Cache, DeepSeek V4, HBF, SLC vs QLC NAND, CXL, NVLink, Tokenomics
10 juli 2026 · 1 uur 4 min
Vik welcomes Val Bercovici from Weka to discuss the rapidly evolving landscape of AI memory and storage. Val explains how Weka's architecture leverages high-bandwidth networks to make storage faster than motherboard DRAM. They dive into KV cache optimizations, the future of NAND flash tiers, and the role of CXL in AI inference. The episode concludes with a look at predictive memory offloading and the AI flywheel. Lees meer
Chapters:
0:00 Welcome Val Bercovici, Weka
1:59 Memory situation and model routing
3:50 KV cache offloading to CMX
6:10 Network faster than motherboard
13:10 Weka as AI memory infrastructure
14:45 Inference market is different
16:06 Memory hierarchy and KV cache
19:40 KV cache optimizations and demand
25:20 DeepSeek's cache read pricing
34:49 NAND flash tiers: SLC vs QLC
43:01 High Bandwidth Flash (HBF)
49:59 CXL versus other interconnectsFollow Chipstrat:
Newsletter: https://www.chipstrat.com
X: https://x.com/chipstratFollow Vik:
Newsletter: https://www.viksnewsletter.com/
X: https://x.com/vikramskrFollow Semi Doped:
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Micron's Record Profits, Apple's CXMT Plea: AI is Eating All the Memory
3 juli 2026 · 51 min
Austin and Vik break down the current memory crisis, where AI demand is driving unprecedented profits for memory makers like Micron, while simultaneously causing inflation and price hikes for consumer electronics. They discuss how even premium brands like Apple are struggling to secure supply, leading them to controversial suppliers. The hosts also explore the long-term implications of AI's insatiable memory appetite and its impact on both data center and consumer markets. Lees meer
Chapters:
0:00 Memory crisis hits
1:20 AI impacting consumers
3:00 AI causing inflation
6:48 Consumer demand drop?
8:49 AI demand inelastic
10:56 Long-term memory outlook
11:02 GoPro's memory woes
12:24 Apple's pricing power
18:20 Apple seeks CXMT DRAM
21:38 Shrinkflation for phones
23:16 Korea's memory investment
26:10 Micron's killing profits
33:00 Why AI needs so much DRAM
40:27 Future of AI training
44:34 Cost-optimizing inferenceFollow Chipstrat:
Newsletter: https://www.chipstrat.com
X: https://x.com/chipstratFollow Vik:
Newsletter: https://www.viksnewsletter.com/
X: https://x.com/vikramskrFollow Semi Doped:
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Qualcomm's HBC Memory, Alphawave, Modular, and more
29 juni 2026 · 1 uur
Qualcomm flew Austin to New York for its investor day, where the communications company laid out a plan to make data center, automotive, and IoT two-thirds of its business by FY29. Austin was in the room and asked Cristiano Amon a question on the record. Vik watched the whole thing on YouTube. Together they break down what actually changed. Lees meer
The technical centerpiece is High Bandwidth Compute (HBC): stacking LPDDR on top of logic to expose the whole face of the chip for interconnects, claiming up to 100x more lanes and a path around the HBM bandwidth bottleneck. Austin and Vik dig into what's really under that memory, why "no advanced packaging needed" just moves the hard problem somewhere worse, and how it compares to d-Matrix. And as Austin put it: don't let anyone tell you HBM is dead. MOAR memory.
Then the roadmap: the AI200/250/300 accelerators, the C1000 server CPU (5 GHz, 250+ cores, Meta as a customer), the Alphawave and Modular acquisitions, and Chris Lattner's Mojo.
The most interesting takeaway might not be the data center at all. Qualcomm's edge play — AI-defined vehicles, cars as token generators, and a $1T robotics opportunity by 2040 — could be where High Bandwidth Compute matters most.
Chapters:
0:00 Communications? That's just the start
4:08 Inside Qualcomm's investor day
9:16 Can Qualcomm build a data center business?
13:09 Disaggregated inference opens the door
17:57 High Bandwidth Compute: memory on the XPU
30:29 "No advanced packaging" just moves the problem
36:20 The roadmap, Alphawave, and Modular
46:00 The C1000 CPU and the agentic shortage
50:40 Cars as token generators, the $1T robotics bet
57:32 The memory market: MOARFollow Semi Doped:
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Vik's Paid Substack: https://www.viksnewsletter.com
Austin's Paid Substack: https://www.chipstrat.com -
Advanced Packaging, TSMC CoWoS, Intel EMIB
19 juni 2026 · 1 uur 9 min
New episode: Advanced packaging for AI chips, from wire bonds to TSMC CoWOS and Intel EMIB. Lees meer
Packaging is no longer an afterthought. It is the chip, and Intel's EMIB challenges TSMC's CoWOS.
Three CoWOS flavors: silicon, organic RDL, local bridges
EMIB embeds tiny bridges into the substrate, no interposer
EMIB-T and EMIB-M add through-silicon vias and power capacitors
Google is booking 3M TPUs on EMIB via MediaTek by 2028
Package sizes keep climbing: 5.5x reticle today, 40x ahead
This episode is brought to you by SambaNova. Try SambaNova's fast inference today at the SambaNova Dashboard!
Connect with Vik and Austin via a daily free newsletter:
https://www.semidoped.comVik's Paid Substack: https://www.viksnewsletter.com
Austin's Paid Substack: https://www.chipstrat.comChapters:
(0:00) "There Is No Chip Without the Packaging"
(0:28) Intro and SpaceX IPO Day
(5:15) What We're Covering: CoWOS, EMIB, Google
(7:40) Simple Packaging: Wire Bonds to Flip Chip
(17:07) What Makes Packaging "Advanced"
(33:44) CoWOS: Three Flavors Explained
(45:30) EMIB: Intel's Embedded Bridge Approach
(52:47) EMIB-T and EMIB-M
(57:31) CoWOS vs. EMIB Trade-offs
(1:02:18) Google's 3M TPU EMIB Order -
Computex Mania 2026: Optics and Power
12 juni 2026 · 48 min
Austin and Vik discuss their recent experience at Computex, where they met for the first time in person after six months of podcasting together. Lees meer
They share insights about the massive show, the people they connected with, and the exciting developments in AI hardware and interconnect technology.
Connect with Vik and Austin via a daily free newsletter:
https://www.semidoped.comVik's Paid Substack: https://www.viksnewsletter.com
Austin's Paid Substack: https://www.chipstrat.comChapters
00:00 Meeting in Person for the First Time
03:05 Experiencing Computex: A Massive Show
05:17 Connecting with the Audience: Real-Life Encounters
06:46 Networking with Industry Leaders
10:42 Keynote Highlights: Marvell's Vision
15:11 The Future of Interconnects: CPO and Beyond
22:54 Exploring Optical Interconnects and Future Technologies
25:56 Micro LED Developments and Future Conferences
27:34 Power Innovations in Data Centers
30:54 Intel's Keynote and New CPU Technologies
36:31 Intel Foundry's Advancements and Industry Implications -
Huawei's Tau Scaling Law: Is the "EUV Killer" Real?
29 mei 2026 · 39 min
Huawei dropped a paper claiming 1.4nm-class performance without EUV, and the internet immediately declared ASML dead and US export controls useless. Austin and Vik recorded one day after Memorial Day to unpack what Huawei actually announced at ISCAS 2026 — and why the "EUV killer" headline gets the story backwards. Lees meer
They walk through the tau scaling law (tau is delay, and the idea is to attack it at the system level instead of the transistor), logic folding via hybrid bonding, the Kirin 2026 that doubles transistor count without shrinking, and who can actually manufacture stacked logic. Then the other tau knobs: a unified memory bus and near-packaged optics. Along the way: BESI vs EV Group, die-to-wafer vs wafer-to-wafer bonding, and why hybrid bonding isn't export-controlled the way EUV is.
The takeaway is the opposite of the headline. Tau scaling is rational engineering under constraint, it's bullish for ASML (two DUV wafers per product, not fewer), and the moment EUV-enabled fabs stack their own advanced-node wafers, the gap widens instead of narrowing. Bullish advanced packaging, bullish EDA and multiphysics.
Chapters:
0:00 The "EUV killer" paper that broke the internet
2:28 What Huawei actually announced at ISCAS
4:00 Tau scaling: optimize delay, not transistors
8:58 The equation and the 10x AI claim
11:05 Logic folding: stacking logic on logic
17:24 Who builds it, and can hybrid bonding be banned?
24:16 Why this is bullish for ASML
29:49 The other tau knobs: memory and optics
35:18 Takeaways: packaging, EDA, multiphysicsFollow Semi Doped:
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Sign up: https://www.semidoped.com/Follow Chipstrat:
Newsletter: https://www.chipstrat.com
X: https://x.com/chipstratFollow Vik:
Newsletter: https://www.viksnewsletter.com
X: https://x.com/vikramskr -
Lithography Masterclass
22 mei 2026 · 1 uur 3 min
Spend one hour here and you've caught up on the entire arc of semiconductor lithography. Austin and Vik run a masterclass on the technology that decides who gets to make leading-edge chips, and why so few companies can afford to. Lees meer
The thread is economics. An EUV machine runs about $400 million, a new fab needs roughly 15 of them, and the total bill clears $20-30 billion before a single wafer ships. Austin and Vik trace the whole story: Rock's Law and the cost of a fab, what it actually takes to build one, the evolution from 193nm DUV through multi-patterning to 13.5nm EUV, how ASML generates EUV light by exploding falling tin droplets, and the move to high NA and its mirrors. Along the way, the fun history — i-line, krypton fluoride, immersion lithography, and the engineer who started it all by flipping a microscope upside down.
Then the part that matters most: where lithography goes next. Two startups, xLight and Substrate, are attacking the cost problem from first principles. xLight wants to decouple the light source from the scanner with a free-electron laser and sell photons as a service. Substrate wants to skip EUV entirely and revive X-ray lithography. If either works, the economics of who can build a fab change completely.
Chapters:
0:00 The 13F panic, and today's topic
2:23 Why the real story is economics, not physics
6:18 Austin in the clean room: graphene and bunny suits
10:06 Rock's Law and the $20 billion fab
18:08 DUV, the Sharpie, and a history of light
24:58 Multi-patterning, explained with a football field
34:45 How EUV makes 13.5nm light from tin droplets
41:14 High NA, anamorphic optics, and the half-field tax
46:45 The startups rethinking lithography: xLight and SubstrateRelevant reading:
Chipstrat — The economics of lithography: https://www.chipstrat.com/p/lithography-economics
Chipstrat — xLight and photons as a service: https://www.chipstrat.com/p/photons-as-a-service
Chipstrat — Substrate and X-ray lithography: https://www.chipstrat.com/p… -
Cerebras IPO
15 mei 2026 · 51 min
Cerebras IPO is the only thing to talk about this week. 🔥 Lees meer
IPO prices at $185/share. Pops nearly 70% right after. The first wafer-scale chip company to make it public — after a 40-year curse killed every prior attempt.
A water-cooler-style convo on what Cerebras actually builds, why a 23 kW wafer is a power and cooling nightmare, why 44 GB of SRAM is both the magic and the wall for LLM inference, and the cursed Trilogy Systems saga that Gene Amdahl tried — and failed — to pull off in 1983.
Why does Cerebras leave the whole wafer intact instead of dicing it? How do they route around defects to harvest ~900K working cores out of ~1M? Why is power delivery vertical, and why does the wafer literally expand a tenth of a millimeter when it heats up? What does the OpenAI deal actually buy — wafers, or tokens? And why does that distinction matter?
Chapters:
0:00 Cold open: 23 kW per wafer
0:15 Cerebras IPO day at $185
2:39 What's a wafer-scale engine
10:30 Power, cooling, and thermal expansion
18:12 The 44 GB wall
26:35 The Trilogy Systems curse
32:11 Supercomputing → training → inference
39:36 The OpenAI deal and the Wild WestRelevant reading:
Vik's Substack post on the Cerebras IPO and OpenAI deal: https://www.viksnewsletter.com/Follow Chipstrat:
Newsletter: https://www.chipstrat.com
X: https://x.com/austinsemisFollow Vik:
Newsletter: https://www.viksnewsletter.com/
X: https://x.com/vikramskrFollow Semi Doped:
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Sign up: https://www.semidoped.com/ -
Gimlet's Cross-Vendor Inference Cloud
12 mei 2026 · 49 min
Gimlet Labs runs an inference cloud built on heterogeneous silicon. Their software traces a PyTorch workload, segments it into its component parts, and schedules each piece onto the best-suited hardware — connecting chips from different vendors on a single high-speed fabric. Lees meer
In this interview, Gimlet co-founder Natalie Serrino and former Intel executive Beltir walk through the architecture (graph trace, optimal split points, lowering each segment to TensorRT on NVIDIA and equivalents elsewhere), the three customer segments they sell into (frontier labs, sovereign clouds, AI natives), and a concrete demo: on GPT-OSS 120B at 8K input / 1K output, running the speculative decoder on a d-Matrix Corsair card while NVIDIA B200s handle the verifier shifts the throughput-vs-interactivity Pareto frontier roughly 4× over GPU-only speculative decode.
The most surprising takeaway: most Neoclouds gave significant equity to a single silicon vendor in exchange for capacity. Hardware amortization is around 70% of their annual costs, and the equity terms prevent them from diversifying their silicon. So the only software innovation they can ship is disaggregation on top of one vendor's stack — never across vendors. Gimlet's two-track model (deploying orchestration software inside customer data centers, plus running their own Neocloud built on mixed silicon) is the answer to that constraint.
Read the full transcript on Chipstrat.
Chapters:
0:00 Intro and the chips no one's connected before
0:33 Inference cloud for agents
1:02 From Intel to Gimlet
2:14 The case for heterogeneous inference
4:03 Disaggregating inference by resource profile
6:24 Tracing PyTorch into a schedulable graph
8:08 Connecting chips never connected before
10:52 CPUs as the agentic workhorse
12:01 Tool calls in the same data center as the LLM
13:21 Latency vs throughput on a shared fabric
14:57 Three customer buckets
15:54 Sovereigns: make an API call, not a porting project
19:37 "Cracked software is the platfo… -
Power as the Next Physics Wall for AI
8 mei 2026 · 42 min
What's common to optics and power that ruins everything in the era of AI? Lees meer
Resistance.
The same physics that drove interconnects to optics is now driving low-voltage power delivery up to 800V. Austin Lyons (Chipstrat) and Vik Sekar (Vik's Newsletter) unpack it using the Kyber rack as an example.
At 600kW and 48V, you're pushing 12,500 amps through a single rack. Power loss scales with I². The math doesn't work. The fix is 800V — and the parts come straight from the EV traction inverter ecosystem (SiC, GaN, IGBTs).
We cover the full grid-to-GPU power conversion chain (substation, utility room, PSU, intermediate bus converter, VRM), why vertical power delivery is the CPO equivalent for power, and why the power industry is a much wider open problem than optics or HBM. Plus the new topology fight: 800V → 48V (reuse the existing 48V infrastructure) vs 800V → 6V (skip 48V entirely, like TI and Navitas are pushing).
We also touch Coherent's six-inch indium phosphide ramp at Järfälla, Sweden, and why margins are the real read-through next quarter.
Relevant reading:
Vik's Substack post on power: https://www.viksnewsletter.com/p/power-delivery-as-the-next-physics-wall
Google TPU 8i / 8t blog (Boardfly deep dive): https://cloud.google.com/blog/products/compute/tpu-8t-and-tpu-8i-technical-deep-diveGet more of Austin and Vik daily, free! Sign up here: https://www.semidoped.com/
Follow Chipstrat:
Newsletter: https://www.chipstrat.com
X: https://x.com/austinsemisFollow Vik:
Newsletter: https://www.viksnewsletter.com/
X: https://x.com/vikramskrChapters
(00:00) Intro
(01:41) Memory tax: inflation, not innovation
(03:46) Boardfly: 16 hops to 7
(05:12) Coherent's six-inch indium phosphide ramp
(12:15) Power is the next physics wall
(15:08) Why 48V breaks at 600kW: 12,500 amps
(23:05) 800V and vertical power delivery: CPO for power
(30:34) Grid to GPU: every stage is a different supply chain
(39:20) 800V → 48V or skip straight to 6V? -
CapEx is just Memory Tax Now, Deepseek V4 NAND impact
4 mei 2026 · 46 min
The hyperscaler memory tax quarter. Lees meer
More CapEx? Pssh. We knew flops needed scaling.
But $25B at Microsoft alone just to pay higher component prices?
A memory tax. That's the news.
NAND? Sold out. HBM? Sold out.
What we cover:
SanDisk revenue +97% sequential.
78% gross margin. Guidance above 80% next quarter.
Samsung HBM4 first to ship. Demand outstripping supply.
DeepSeek v4 goes SSD-centric. KV cache offloads to flash.
Microsoft: $25B of 2026 CapEx is just memory pricing.
Jassy: memory shortage pushes on-prem to AWS.
Qualcomm: mystery custom ASIC. Ships December.
New Semi Doped with @vikramskr and @austinsemis.
Check out our Substacks
- https://www.viksnewsletter.com/
- https://www.chipstrat.com/Chapters:
0:00 Intro and Vik goes full-time
5:15 Earnings week: the memory tax
7:26 Samsung HBM4 and the Gbps race
14:42 Is the memory tax worth it?
17:37 SanDisk and the SunDisk origin
23:22 78% gross margins and 5-year supply lock-ins
29:29 DeepSeek v4 and SSD-centric inference
38:49 Hyperscaler CapEx and the cloud pull
42:49 AI accelerators: TPU, Trainium, MTIA -
Masterclass on Google's TPU v8 Networking
24 april 2026 · 47 min
Google's Cloud Next 2026 keynote? Fire. 🔥 Lees meer
The TPU is now two chips instead of one — 8t for training, 8i for inference — but more interestingly, it's two scale-up networking topologies too.
Austin Lyons (Chipstrat) and Vik Sekar (Vik's Newsletter) walk through what actually changed, one day after the announcement. OCS? Yes. AECs? Yep. Copper? Yep. Optics? Yep.
We cover Virgo (Google's 47 petabit/second scale-out fabric, built entirely on OCS), Boardfly (the new scale-up topology for MoE inference that cuts hop count from 16 to 7), and the 3D torus Google still uses for training.
Why is optical circuit switching the substrate of Google's data center? Why do active electrical cables still carry scale-up traffic inside racks? Why did Google split the CPU layer too, with custom ARM Axion head nodes to keep the TPUs fed?
Along the way we trace the Dragonfly topology lineage to a 2008 paper by John Kim, Bill Dally, Steve Scott, and Dennis Abts. Abts went on to build Groq's rack-scale interconnect before landing at Nvidia.
Chapters:
0:00 Intro
0:21 Two TPUs for two workloads
2:31 HBM, SRAM, and Axion CPUs
7:22 Why networking is the new bottleneck
17:14 Virgo: rebuilding scale-out on optics
25:24 3D torus Rubik's Cube scale-up for training
34:50 Boardfly: scale-up for MoE inference
42:07 Workload-specific everythingFollow Chipstrat:
Newsletter: https://www.chipstrat.com
X: https://x.com/austinsemisFollow Vik:
Newsletter: https://www.viksnewsletter.com/
X: https://x.com/vikramskr -
Meta VP Matt Steiner on Ads Infra, GPUs, MTIA, and LLM-Written Kernels
20 april 2026 · 40 min
Matt Steiner, VP of Monetization Infrastructure, Ranking & AI Foundations at Meta, walks through how Meta's ad system actually works, and why the infrastructure behind it differs from what you'd build for LLMs. Lees meer
We cover Andromeda (retrieval on a custom NVIDIA Grace Hopper SKU Meta co-designed), Lattice (consolidating N ranking models into one), GEM (Meta's Generative Ads Recommendation foundation model), and the adaptive ranking model, a roughly one-trillion-parameter recommender served at sub-second latency.
We get into why recommender workloads aren't embarrassingly parallel like LLMs (the "personalization blob"), what that means for Meta's MTIA custom silicon roadmap, and how LLM-written kernels (KernelEvolve) flipped the economics of running a heterogeneous hardware fleet. Demand for software engineering has actually gone up as the price has come down. Meta now wants ~100x more optimized kernels per chip.
Read the full transcript at https://www.chipstrat.com/p/an-interview-with-meta-vp-matt-steiner
Chapters:
0:00 Intro and scale
0:39 How Meta's ad system works
2:00 Meta Andromeda and the custom NVIDIA SKU
3:30 Lattice: consolidating ranking models
5:00 GEM, Meta's ads foundation model
6:30 Adaptive ranking for power users
8:17 The scale: 3B DAUs at sub-second latency
9:40 Why longer interaction histories matter
10:45 The anniversary gift analogy
12:57 A decade of compute evolution
15:21 Meta's infra as a CP-SAT problem
16:07 Co-designing Grace Hopper with NVIDIA
17:47 Matching compute shape to workload
18:26 Influencing hardware and software roadmaps
20:23 MTIA: why ads aren't LLMs
22:07 The personalization blob and I/O ratios
26:38 One trillion parameters at sub-second latency
28:26 Heterogeneous hardware trade-offs
29:30 KernelEvolve: LLMs writing custom kernels
33:30 GenAI and recommender systems cross-pollination
35:21 The 2-year infrastructure outlook
37:00 Why demand for software engineering is rising
38:53 How Matt stays on top of it allRelevant re…
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Credo + Dust Photonics, XPO, Nuvacore
17 april 2026 · 38 min
Austin and Vik discuss Credo's acquisition of Dust Photonics, XPO as the new standard for scale-out (maybe instead of CPO?) and some thoughts about Nuvacore entering the CPU scene for agentic AI. Lees meer
Gavin Baker's tweet: https://x.com/GavinSBaker/status/2044410644301046031?s=20
Vik's Substack: https://www.viksnewsletter.com
Austin's Substack: https://www.chipstrat.comChapters
00:00 Introduction to the Semiconductor Landscape
02:49 The Rise of Nuvacore and CPU Innovations
05:27 The Demand for CPUs in the AI Era
07:59 Photonics: The Next Frontier in Semiconductors
10:26 Credo's Acquisition of Dust Photonics
13:12 Vertical Integration in Semiconductor Companies
15:15 The Future of Copper and Optical Technologies
20:28 The Evolution of AI Training Models
25:28 Innovations in Optical Interconnects
31:10 The Future of Data Center Connectivity
36:56 Strategic Implications in the Optical Ecosystem -
Is Intel Finally Back with a $300B market cap? OpenClaw can Dream?
10 april 2026 · 34 min
In this episode, Austin and Vik discuss if Intel is finally back with CPU partnerships with Google, and heterogeneous inference with SambaNova, while market cap soars above $300B. Vik tries to get his OpenClaw instance to dream every night. Lees meer
Chapters
00:00 Anthropic's New Direction: Chip Development
02:30 Navigating Subscription Changes and Token Costs
05:25 Exploring Alternative AI Models
08:10 The Economics of AI: Rent vs. Buy
10:56 Intel's Resurgence and Market Dynamics
15:23 Intel's Strategic Partnerships and Market Positioning
19:37 The Role of IPUs in Modern Computing
25:08 Coexistence of x86 and ARM Architectures
29:55 Innovations in Chip Architecture and Future Prospects -
Reiner Pope (MatX): Designing AI Chips From First Principles for LLMs
9 april 2026 · 39 min
Reiner Pope is the co-founder and CEO of MatX, the startup building chips designed from first principles for LLMs. Before MatX, Reiner was on the Google Brain team training LLMs, and his co-founder Mike Gunter was on the TPU team. They left Google one week before ChatGPT was released. Lees meer
A counterintuitive throughput insight from the conversation:
“Low latency means small batch sizes. That is just Little’s law. Memory occupancy in HBM is proportional to batch size. So you can actually fit longer contexts than you could if the latency were larger. Low latency is not just a usability win, it improves throughput.”
We get into:
• The hybrid SRAM + HBM bet, and why pipeline parallelism finally works
• Overcoming the CUDA moat
• Why frontier labs are willing to bet on an AI ASIC startup
• Memory-bandwidth-efficient attention, numerics, and what MatX publishes (and what it does not)
• Why 95% of model-side news is noise for chip design
• Why sparse MoE drives MatX to “the most interconnect of any announced product”
• How MatX uses AI for its own chip design
• The biggest challenges ahead
Chapters:
00:00 “We left Google one week before ChatGPT”
00:24 Intro: who is MatX
01:17 Origin story: leaving Google for LLM chips
02:21 GPT-3 and the “too expensive” problem
04:25 Why buy hardware that is not a GPU
05:52 Overcoming the CUDA moat
08:46 Early investors
09:35 The name MatX
09:59 The chip: matrix multiply + hybrid SRAM/HBM
12:11 Why pipeline parallelism finally works
14:22 Reading papers and Google going dark
15:20 Research agenda: attention and numerics
17:06 Five specs and meeting customers where they are
19:24 Why frontier labs are the natural first customer
20:32 Workloads: training, prefill, decode
22:18 Little’s law and the throughput case for low latency
24:29 Interconnect and MoE topology
26:35 Inside the team: 100 people, full stack
28:32 Agentic AI: 95% noise for hardware
30:35 KV cache sizing in an agentic world
32:11 How MatX uses AI…
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$300M for 70K Viewers | Intel x Elon, OpenAI x TBPN, Citrini's Strait of Hormuz Stunt
7 april 2026 · 36 min
Intel Foundry just partnered with Elon Musk’s Terafab. What is Terafab anyway, why vertically integrated fabs make sense but the economics don’t (yet!), and what Intel is doing here (hint: no idea). Lees meer
Then: OpenAI acquires TBPN for an estimated $100-300M. Not sure why, but the more interesting thing is the value of niche audiences when five companies control a trillion dollars in AI capex.
And finally, Citrini Research sent an analyst to the Strait of Hormuz with a Pelican case full of spy gear, $15K cash, and Cuban cigars. The most unhinged research trip in Substack history.
Austin Lyons — Chipstrat (https://chipstrat.com) Vik Sekar — Vik's Newsletter (https://www.viksnewsletter.com)
Subscribe for weekly episodes on semiconductors, AI, infrastructure, and the business of chips.
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NVIDIA's Marvell Strategy, Is Memory Different This Time?, Intel's Ireland Fab
3 april 2026 · 42 min
In this episode, Austin and Vik analyze NVIDIA's $2 billion investment in Marvell NVLink Fusion, exploring its implications for AI infrastructure, interconnect protocols, and the broader chip ecosystem. They also discuss the current memory market surge, DRAM pricing, and Intel's strategic fab buyback, providing deep insights into industry trends and future directions. Lees meer
On Substack
Vik: https://www.viksnewsletter.com/
Austin: https://www.chipstrat.com/Chapters
00:00 NVIDIA's $2 Billion Investment in Marvell
20:11 The Memory Market Crisis
20:16 The Future of Memory Pricing and Consumer Impact
22:55 The Cycle of Supply and Demand in Memory
27:23 AI's Impact on Memory Demand
31:46 Long-Term Agreements and Market Stability
35:07 Intel's Strategic Fab Buyback
40:44 Monopoly Analogy: Intel's Market Strategy -
ARM AGI CPU has entered the chat, TurboQuant thrashes memory stocks
27 maart 2026 · 52 min
In this episode, Austin and Vik analyze recent developments in GloFo patent lawsuits, the impact of TurboQuant on AI inference, and ARM's strategic move into silicon for agentic AI workloads. Lees meer
Read Vik's substack: https://www.viksnewsletter.com
Read Austin's substack: https://www.chipstrat.comChapters
00:00 Patent Wars in Semiconductor Industry
07:14 Understanding TurboQuant and Its Implications
24:42 Innovations in Memory Management
28:00 The Rise of ARM AGI CPUs
32:56 Agentic AI and CPU Compatibility
39:54 Performance Metrics in Agentic AI
44:52 ARM's Market Timing and Challenges -
MicroLEDs Ain’t Dead, Micron Snags Vera Rubin
20 maart 2026 · 43 min
Austin and Vik break down a packed week in semiconductors, covering GTC, OFC, and Micron earnings. The conversation kicks off with Jensen Huang's bold claim that engineers should spend $250K/year on AI tokens, and whether companies will buy tokens or token generators (i.e., on-prem hardware like the Dell Pro Max with GB300). They dig into the CapEx vs OpEx tradeoffs, data security concerns, and how sharing GPU resources might end up looking a lot like the old EDA license model. Lees meer
Next up: Micron crushed earnings and appears to be designed into Vera Rubin for HBM4 — despite months of rumors saying otherwise. Austin and Vik unpack the nuance around HBM pin speeds, memory node base dies, and what Micron's massive new fab investments in Taiwan, Singapore, Idaho, and New York mean for the memory cycle.
The back half of the episode dives into optical interconnects for AI scale-up. A new industry consortium (OCI-MSA) has formed with Meta, Broadcom, NVIDIA, and OpenAI to standardize optical components. Vik explains why traditional indium phosphide lasers might be overkill for short-reach scale-up, and makes the case for micro LEDs — a "slow but wide" approach that could fill the gap between copper and conventional optics. They also touch on Credo's expanding product portfolio (and the infamous purple-to-orange cable saga), plus Lumentum's new VCSEL work for scale-up.
Vik - https://www.viksnewsletter.com/
Austin - https://www.chipstrat.com/CHAPTERS
0:00 Intro & GTC/OFC Conference Overload
2:09 Jensen's $250K Token Budget Per Engineer
5:08 On-Prem Inference vs. Cloud Token Spending (Dell Pro Max, CapEx vs OpEx)
6:44 Sharing GPU Resources Like EDA Licenses
8:16 Data Security & On-Prem Privacy Concerns
9:53 Matthew Berman's Fine-Tuned Open Claw Agent
10:35 Vik Sets Up Open Claw on a Home Server
11:53 Always Be Clauden (ABC) – Managing Agents from Your Phone
13:34 Micron Earnings & HBM4 in Vera Rubin
16:39 HBM Pin Speeds & the Micron Design-In Debate
20:17 Micron's New Fab I… -
Quick Takes: Nvidia Keynote at GTC
17 maart 2026 · 59 min
Vik and Austin unpack the Nvidia GTC keynote with fresh, top-of-mind takes while trying to breakdown key announcements, what matters and what doesn't. They discuss Groq's LPX, optics+copper for scale up, new CPU requirements, CPO for networking, and what agents means for software, and much, much, more. Lees meer
Check out Austin's substack: https://www.chipstrat.com
Check out Vik's substack: https://www.viksnewsletter.comChapters
00:00 Introduction and Keynote Context
03:18 Keynote Highlights and Gaming Innovations
06:18 Generative AI: The Three Eras
09:28 Inference: The New Revenue Generator
12:21 NVIDIA's Tiered Approach to AI Models
15:30 The Grok Chip and Its Role
18:35 Vera Rubin System: A Full Data Center
21:18 CPU Demand and Performance
24:31 Networking Innovations and Future Directions
32:32 Innovations in PCB Technology
34:06 Scaling GPU Systems
36:57 Understanding the STX Rack and AI Storage
38:23 The Rosa CPU and Its Significance
40:07 Digital Twin Platforms and AI Factories
43:53 NVIDIA's New Software Innovations
47:09 The Future of Token Budgets in AI
54:15 Balancing CapEx and OpEx in AI Deployments -
Meta's Inference Accelerator & Applied Optoelectronics (AAOI)
13 maart 2026 · 1 uur 2 min
Austin recaps moderating an agentic AI panel at Synopsys Converge, then gives an in-depth technical breakdown of Meta's MTIA custom silicon. Why they're building it, how chiplets let them ship a new chip every 6 months, and how the roadmap is shifting toward gen AI inference. Vik digs into Applied Optoelectronics (AAOI), the vertically integrated Texas laser shop whose stock went from $1.48 to $100+, and whether history is about to rhyme. Lees meer
Austin Lyons: https://www.chipstrat.com
Vik Sekar: https://www.viksnewsletter.com/Topics covered:
• Agentic AI in chip design — how it changes roles for junior and senior engineers
• Optical circuit switching and what it means for Arista's business model
• Meta's ad-serving pipeline: Andromeda, Lattice, and the GEM foundation model
• Why custom silicon (MTIA) makes sense at Meta's scale
• MTIA chiplet strategy — 4 generations in 2 years
• AAOI's vertical integration, Amazon's $4B warrant deal, and the 2017 parallelChapters:
0:00 Intro
1:26 Synopsys Converge — Agentic AI Panel
9:44 Vik's Article: Optical Circuit Switching & Arista
14:43 Meta MTIA — A New Chip Every 6 Months
21:32 Why Custom Silicon Makes Sense for Meta
27:22 MTIA Chiplet Strategy & Roadmap
33:56 Gen AI Fits Meta's Business Model
36:31 How Meta Ships Chips So Fast
40:30 Applied Optoelectronics (AAOI) Deep Dive
45:02 Amazon's $4B Warrant Deal
48:54 Can AAOI's Lasers Compete with Lumentum?
53:16 AAOI's Aggressive Capacity Buildout
55:35 History Rhymes: AAOI's 2017 Boom & Bust
1:00:55 Wrap-Up#semiconductors #chips #tech #meta #MTIA #AAOI #optics #inference #AI
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The Great Optics-Copper Crossroads
7 maart 2026 · 48 min
This week, Austin and Vik break down the optics vs. copper debate that rocked semis this week. Nvidia dropped $4 billion on Lumentum and Coherent, Credo posted a blowout quarter betting on copper, and then Hock Tan shocked everyone claiming 400G per lane works over copper in Broadcom’s labs — potentially pushing CPO out to 2030+. Plus, Vik’s 4D chess conspiracy theory on why Hock Tan is talking up copper when Broadcom is a CPO company. Lees meer
Like, subscribe, and drop your thoughts on the copper vs. optics debate in the comments!
Subscribe to our newsletters:
* Chipstrat by Austin Lyons — chipstrat.com
* Vik’s Semiconductor Newsletter by Vik Sekar — viksnewsletter.comChapters
(00:00) - Newsletter Plugs: Groq LPUs & Broadcom’s Laser Business
(03:15) - Dynamo & the Rise of Workload-Specific Hardware
(08:04) - Austin’s Broadcom Laser Deep Dive
(09:53) - The Week’s Whiplash: Optics Monday, Copper Wednesday
(17:50) - Why Nvidia Invested $4B: Geopolitics, Supply & the HBM Playbook
(24:15) - CPO Lasers & Optical Circuit Switches
(26:16) - Credo Earnings: 200% YoY Growth & the Copper Bull Case
(31:09) - Reliability, AECs & Oracle’s GPU Cluster Problem
(35:48) - Credo’s Optics Play: Micro-LED Active Cables & the CPO Timing Risk
(38:45) - Broadcom Earnings: Hock Tan’s Copper Bombshell
(43:34) - Customer-Owned Tooling: Hock Tan Says “Good Luck”
(44:25) - Vik’s 4D Chess Theory: Why Hock Tan Talks Up Copper
(47:03) - Wrap-Up: It’s Both — The Real Question Is Timing -
Optical Supply Chain: What would you buy?
27 februari 2026 · 1 uur 2 min
This week, we move from optics technology to optics companies. We walk the AI optical supply chain from bottom to top. Main debate: Who has a moat? Who is already priced for perfection? *Not investment advice, do your own due diligence* Lees meer
AXTI - Indium phosphide substrate supplier. Critical bottleneck in the laser stack. Major China export-control risk. Massive stock run vs thin earnings.
Tower Semiconductor - Leading silicon photonics foundry. 5x capacity expansion with customer prepayments. Strong process lock-in. Pure-play optics exposure.
GlobalFoundries - 300mm monolithic photonics platform + Chips Act support. Optics growing fast but still small piece of overall business.
Lumentum - Dominant EML laser supplier. Explosive AI demand. Strong technical moat. Valuation and capex sensitivity are key risks.
Coherent - Vertically integrated from substrate to module. 6-inch InP push could lower costs structurally. Execution and margin mix matter.
Fabrinet - Optics assembly partner. High NVIDIA exposure. Scales with industry, but dependent on upstream supply.
Corning - AI data centers require far more fiber than traditional cloud. $6B Meta deal adds visibility. Timing of scale-up optics is the swing factor.
Timestamps
00:01 Intro
06:59 AXT $AXTI
13:38 Tower Semiconductor $TSEM
23:58 GlobalFoundries $GFS
32:43 Lumentum $LITE
39:38 Coherent $COHR
47:09 Fabrinet $FN
54:07 Corning $GLWAustin's Substack: https://www.chipstrat.com/
Vik's Substack: https://www.viksnewsletter.com/
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Optical Networking Supercycle - ALL the Tech You NEED to know
20 februari 2026 · 46 min
Austin and Vik delve into the evolving landscape of optics and networking, particularly in relation to AI and data centers. Lees meer
The conversation covers various scales of networking, including scale across, scale out, and scale up, while also addressing the demand-supply dynamics in laser manufacturing and the future of optical circuit switches.
The episode highlights the technological advancements and market opportunities in the optics sector, emphasizing the significance of these developments for the future of AI.
Takeaways
Silicon photonics is becoming crucial for data center connectivity.
Optics is essential for overcoming copper's limitations in speed and distance.
Scale across technology is vital for connecting data centers.
Scale out optics is the standard for connecting GPUs between racks.
Co-packaged optics can reduce energy consumption in data centers.
The scale up market for optics is emerging as a new opportunity.
Indium phosphide wafers are a critical bottleneck in laser manufacturing.
Optical circuit switches are gaining traction in data centers.
2026 is anticipated to be a pivotal year for optical networking.
Chapters
00:00 Introduction to AI and CPU Bottlenecks
03:00 The Rise of Silicon Photonics
06:01 Understanding Optical Networking and Data Centers
08:49 Scale Across: Connecting Data Centers
11:56 Scale Out: Optimizing Data Center Connectivity
14:53 Scale Up: The Future of GPU Connectivity
23:32 The Shift from Copper to Optical Connections
26:13 Challenges and Reliability of Lasers
30:47 Understanding Co-Packaged Optics
34:17 Market Dynamics: Demand and Supply of Lasers
40:46 Emerging Technologies: Optical Circuit SwitchesCheck out Austin's Substack: https://www.chipstrat.com
Check out Vik's Substack: https://www.viksnewsletter.com -
Memory Mayhem & AI Capex Madness
13 februari 2026 · 59 min
In this episode of the Semi Doped podcast, Austin and Vik delve into the current state of the semiconductor industry, focusing on the memory crisis driven by increasing demand from AI applications. They discuss the implications of rising memory prices, the impact of hyperscaler spending on the market, and the strategic moves of major players like Google, Microsoft, Meta, and Amazon in the AI landscape. Lees meer
Takeaways
Memory prices are skyrocketing, impacting consumer electronics.
The memory crisis is affecting the production of lower-end devices.
DRAM prices have doubled in a single quarter, creating challenges for manufacturers.
Nanya Tech's revenue growth indicates a booming memory market.
AI applications are driving unprecedented demand for memory.
Hyperscalers are significantly increasing their capital expenditures for AI infrastructure.
The integration of AI into advertising is reshaping business models for companies like Google and Meta.
Chapters
00:00 The State of Memory in Semiconductors
03:08 Nvidia's GPU Dilemma and Market Dynamics
06:13 The Impact of AI on Memory Demand
09:08 NAND Flash and Context Memory Trends
11:59 The Future of Memory Supply and Demand
15:12 AI Infrastructure and CapEx Spending
17:47 Google's Strategic Investments in AI
20:58 The Advertising Business Model and AI Integration
30:26 Revenue vs. Expenses: A Balancing Act
31:08 The Future of TPUs vs. GPUs in Cloud Computing
35:31 Microsoft vs. Google: AI Investments and Market Reactions
38:22 AI Integration in Enterprises: Microsoft’s Unique Position
39:57 The Power of Microsoft’s Reach in AI
40:30 GitHub: A Hidden Gem for Microsoft’s AI Strategy
43:52 Meta’s AI Strategy: Advertising and Revenue Growth
51:18 Amazon’s Massive CapEx: Implications for the Future
54:00 Looking Ahead: Predictions for 2027 and BeyondCheck out Austin's substack: https://www.chipstrat.com/
Check out Vik's substack: https://www.viksnewsletter.com/ -
The future of financing AI infrastructure with Wayne Nelms, CTO of Ornn
10 februari 2026 · 41 min
In this episode, Vik and Wayne Nelms discuss the emerging financial exchange for GPU compute, exploring its implications for the AI infrastructure market. They discuss the value of compute, pricing dynamics, hedging strategies, and the future of GPU and memory trading. Lees meer
Wayne shares insights on partnerships, the depreciation of GPUs, and how inference demand may reshape hardware utilization. The conversation highlights the importance of financial products in facilitating data center development and optimizing profitability in the evolving landscape of compute resources.
Takeaways
Wayne Nelms is the CTO of Ornn, focusing on GPU compute as a commodity.
The value of compute is still being defined in the market.
Hedging strategies are essential for managing compute costs.
The pricing of GPUs varies significantly across providers.
Memory trading is becoming a crucial aspect of the compute market.
Partnerships can enhance trading platforms and market efficiency.
Depreciation of GPUs is not linear and varies by use case.
Inference demand may change how GPUs are utilized in the future.
Transparency in pricing benefits smaller players in the market.
Financial products can facilitate data center development and profitability.
Chapters
00:00 Introduction to GPU Compute Futures
03:13 The Value of Compute in Today's Market
05:59 Understanding GPU Pricing Dynamics
08:46 Hedging and Futures in Compute
11:52 The Role of Memory in AI Infrastructure
15:14 Partnerships and Market Expansion
17:46 Depreciation and Residual Value of GPUs
20:57 Future of Data Centers and Compute Demand
24:01 The Impact of Financialization on AI Infrastructure
27:04 Looking Ahead: The Future of Compute Markets
Keywords
GPU compute, financial exchange, futures market, data centers, AI infrastructure, pricing strategies, hedging, memory trading, Ornn
Follow Wayne Nelms (@wayne_nelmz on X)
Check out Ornn's website: https://www.ornnai.com/
Check out Vik's Substack: https://www.viksn…
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A New Era of Context Memory with Val Bercovici from WEKA
6 februari 2026 · 54 min
Vik and Val Bercovici discuss the evolution of storage solutions in the context of AI, focusing on Weka's innovative approaches to context memory, high bandwidth flash, and the importance of optimizing GPU usage. Lees meer
Val shares insights from his extensive experience in the storage industry, highlighting the challenges and advancements in memory requirements for AI models, the significance of latency, and the future of storage technologies.
Takeaways
Context memory is crucial for AI performance.
The demand for memory has drastically increased.
Latency issues can hinder AI efficiency.
High bandwidth flash offers new storage capabilities.
Weka's Axon software enhances GPU storage utilization.
Token warehouses can significantly reduce costs.
Augmented memory grids improve memory access speeds.
Networking innovations are essential for AI storage solutions.
Understanding memory hierarchies is vital for optimization.
The future of storage will involve more advanced technologies.
Chapters
00:00 Introduction to Weka and AI Storage Solutions
05:18 The Evolution of Context Memory in AI
09:30 Understanding Memory Hierarchies and Their Impact
16:24 Latency Challenges in Modern Storage Solutions
21:32 The Role of Networking in AI Storage Efficiency
29:42 Dynamic Resource Utilization in AI Networks
30:04 Introducing the Context Memory Network
31:13 High Bandwidth Flash: A Game Changer
32:54 Weka's Neural Mesh and Storage Solutions
35:01 Axon: Transforming GPU Storage into Memory
39:00 Augmented Memory Grid Explained
42:00 Pooling DRAM and CXL Innovations
46:02 Token Warehouses and Inference Economics
52:10 The Future of Storage InnovationsResources
Manus AI $2B Blog: https://manus.im/blog/Context-Engineering-for-AI-Agents-Lessons-from-Building-Manus
Also listen to this podcast on your favorite platform. https://www.semidoped.fm/
Check out Vik's Substack: https://www.viksnewsletter.com/
Check out Austin's Substack: https://www.chipstrat.com/ -
OpenClaw Makes AI Agents and CPUs Get Real
3 februari 2026 · 48 min
Austin and Vik discuss the emerging trend of AI agents, particularly focusing on Claude Code and OpenClaw, and the resulting hardware implications. Lees meer
Key Takeaways:
2026 is expected to be a pivotal year for AI agents.
The rise of agentic AI is moving beyond marketing to practical applications.
Claude Code is being used for more than just coding; it aids in research and organization.
Integrating AI with tools like Google Drive enhances productivity.
Security concerns arise with giving AI agents access to personal data.
Local computing options for AI can reduce costs and increase control.
AI agents can automate repetitive tasks, freeing up human time for creative work.
The demand for CPUs is increasing due to the needs of AI agents.
AI can help summarize and organize information but may lack deep insights.
The future of AI will involve balancing automation with human oversight.
Chapters
(00:00) Introduction: Why 2026 may be the year of AI agents
(01:12) What people mean by agents and the OpenClaw naming chaos
(02:41) Agents behaving badly: crypto losses and social posting
(03:38) Claude Code as a research tool, not a coding tool
(05:54) Terminal-first workflows vs GUI-based agents
(07:44) Connecting Claude Code to Gmail, Drive, and Calendar via MCP
(09:12) Token waste, authentication friction, and workflow optimization
(10:54) Automating newsletter ingestion and research archives
(12:33) Giving agents login credentials and security tradeoffs
(13:50) Filtering signal from noise with topic constraints
(16:36) AI-driven idea generation and its limitations
(17:34) When automation effort is not worth it
(19:02) Are agents ready for non-technical users?
(20:55) Why OpenClaw should not run on your personal laptop
(21:33) Safe agent deployment: VPS vs local servers
(23:33) The true cost of agents: infrastructure plus inference
(24:18) What OpenClaw adds beyond Claude Code
(26:53) Agents require managerial thinking and self-awareness
(28:18) Local inference vs cloud… -
An Interview with Microsoft's Saurabh Dighe About Maia 200
28 januari 2026 · 53 min
Maia 100 was a pre-GPT accelerator.
Maia 200 is explicitly post-GPT for large multimodal inference. Lees meerSaurabh Dighe says if Microsoft were chasing peak performance or trying to span training and inference, Maia would look very different. Higher TDPs. Different tradeoffs. Those paths were pruned early to optimize for one thing: inference price-performance. That focus drives the claim of ~30% better performance per dollar versus the latest hardware in Microsoft’s fleet.
Intereting topics include:
• What “30% better price-performance” actually means
• Who Maia 200 is built for
• Why Microsoft bet on inference when designing Maia back in 2022/2023
• Large SRAM + high-capacity HBM
• Massive scale-up, no scale-out
• On-die NIC integrationMaia is a portfolio platform: many internal customers, varied inference profiles, one goal. Lower inference cost at planetary scale.
Chapters:
(00:00) Introduction
(01:00) What Maia 200 is and who it’s for
(02:45) Why custom silicon isn’t just a margin play
(04:45) Inference as an efficient frontier
(06:15) Portfolio thinking and heterogeneous infrastructure
(09:00) Designing for LLMs and reasoning models
(10:45) Why Maia avoids training workloads
(12:00) Betting on inference in 2022–2023, before reasoning models
(14:40) Hyperscaler advantage in custom silicon
(16:00) Capacity allocation and internal customers
(17:45) How third-party customers access Maia
(18:30) Software, compilers, and time-to-value
(22:30) Measuring success and the Maia 300 roadmap
(28:30) What “30% better price-performance” actually means
(32:00) Scale-up vs scale-out architecture
(35:00) Ethernet and custom transport choices
(37:30) On-die NIC integration
(40:30) Memory hierarchy: SRAM, HBM, and locality
(49:00) Long context and KV cache strategy
(51:30) Wrap-up